Stateful logic pipeline architecture

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine-grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.