Stateful logic pipeline architecture

Kyosun Kim, Sangho Shin, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine-grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.

Original languageEnglish (US)
Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages2497-2500
Number of pages4
DOIs
Publication statusPublished - Aug 2 2011
Externally publishedYes
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: May 15 2011May 18 2011

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period5/15/115/18/11

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kim, K., Shin, S., & Kang, S. M. (2011). Stateful logic pipeline architecture. In 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (pp. 2497-2500). [5938111] https://doi.org/10.1109/ISCAS.2011.5938111