TY - JOUR
T1 - Reconfigurable stateful nor gate for large-scale logic-array integrations
AU - Shin, Sangho
AU - Kim, Kyosun
AU - Kang, Sung Mo
N1 - Funding Information:
Manuscript received November 8, 2010; revised February 14, 2011; accepted April 4, 2011. Date of publication July 5, 2011; date of current version July 20, 2011. This work was supported in part by the University of California, Merced. This paper was recommended by Associate Editor P. Li. S. Shin and S.-M. Kang are with the Baskin School of Engineering, University of California, Santa Cruz, CA 95064 USA (e-mail: [email protected]; [email protected]). K. Kim is with the Department of Electronic Engineering, University of Incheon, Incheon 406-772, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2011.2158253 Fig. 1. Basic operations in stateful logic. (a) Material implication performed by two simultaneous voltage pulses VCOND and VSET, which are applied to memristive switches P and Q, respectively. (b) Truth table for material implication. (c) NAND operation performed by a three-step schedule. (d) Schedule to execute a NAND operation.
PY - 2011/7
Y1 - 2011/7
N2 - This brief presents a stateful logic gate based on memristive devices that functions as high-fan-in nor gates. The proposed logic structure executes multiple implications concurrently in a single step and thus enables fast logic operations reducing the number of pipeline steps. By mapping the logic units to the field-programmable nanowire interconnect fabric, a reconfigurable 2-D logic array for general-purpose functions can be implemented by configuring nanowire crossbar switches.
AB - This brief presents a stateful logic gate based on memristive devices that functions as high-fan-in nor gates. The proposed logic structure executes multiple implications concurrently in a single step and thus enables fast logic operations reducing the number of pipeline steps. By mapping the logic units to the field-programmable nanowire interconnect fabric, a reconfigurable 2-D logic array for general-purpose functions can be implemented by configuring nanowire crossbar switches.
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U2 - 10.1109/TCSII.2011.2158253
DO - 10.1109/TCSII.2011.2158253
M3 - Article
AN - SCOPUS:79960739050
SN - 1549-7747
VL - 58
SP - 442
EP - 446
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 7
M1 - 5940215
ER -