Power efficient high-speed DAC for wideband communication applications

Jaejin Jung, Sangho Shin, Shin Il Lim, Suki Kim, Sung Mo Kang

Research output: Contribution to journalArticlepeer-review

Abstract

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 ? 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion stepW).

Original languageEnglish (US)
Pages (from-to)421-428
Number of pages8
JournalAnalog Integrated Circuits and Signal Processing
Volume70
Issue number3
DOIs
StatePublished - Mar 2012

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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