Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy

Stephen H. Lewis; R. Ramachandran; W. Martin Snelgrove

doi:10.1109/82.401166

Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy

Stephen H. Lewis
, R. Ramachandran
, W. Martin Snelgrove

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

This paper presents a study of indirect fault testing of digital-correction circuits that operate as a part of analog-to-digital converters with redundancy. Design and test techniques that improve the fault coverage are described. The limitations of these techniques and methods to overcome these limitations are presented.

Original language	English (US)
Pages (from-to)	437-445
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	42
Issue number	7
DOIs	https://doi.org/10.1109/82.401166
State	Published - Jul 1995
Externally published	Yes

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering

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10.1109/82.401166

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@article{7c1bd415d7374e61b91ecbf3df1d30f4,

title = "Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy",

abstract = "This paper presents a study of indirect fault testing of digital-correction circuits that operate as a part of analog-to-digital converters with redundancy. Design and test techniques that improve the fault coverage are described. The limitations of these techniques and methods to overcome these limitations are presented.",

author = "Lewis, \{Stephen H.\} and R. Ramachandran and Snelgrove, \{W. Martin\}",

note = "Funding Information: Manuscript received June 21, 1993; revised August 30, 1994. This work was supported by AT\&T and NSF Grant MIP-9210071. This paper was recommended by Associate Editor V. Gopinathan. S. H. Lewis is with Solid-state Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA. R. Ramachandran is with AT\&T Bell Laboratories, Allentown, PA 18103 USA. W. M. Snelgrove is with the Department of Electrical Engineering, Carleton University, Ottawa, Cntario, Canada K1S 5B6. IEEE Log Number 9412398.",

year = "1995",

month = jul,

doi = "10.1109/82.401166",

language = "English (US)",

volume = "42",

pages = "437--445",

journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",

issn = "1057-7130",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy

AU - Lewis, Stephen H.

AU - Ramachandran, R.

AU - Snelgrove, W. Martin

N1 - Funding Information: Manuscript received June 21, 1993; revised August 30, 1994. This work was supported by AT&T and NSF Grant MIP-9210071. This paper was recommended by Associate Editor V. Gopinathan. S. H. Lewis is with Solid-state Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA. R. Ramachandran is with AT&T Bell Laboratories, Allentown, PA 18103 USA. W. M. Snelgrove is with the Department of Electrical Engineering, Carleton University, Ottawa, Cntario, Canada K1S 5B6. IEEE Log Number 9412398.

PY - 1995/7

Y1 - 1995/7

N2 - This paper presents a study of indirect fault testing of digital-correction circuits that operate as a part of analog-to-digital converters with redundancy. Design and test techniques that improve the fault coverage are described. The limitations of these techniques and methods to overcome these limitations are presented.

AB - This paper presents a study of indirect fault testing of digital-correction circuits that operate as a part of analog-to-digital converters with redundancy. Design and test techniques that improve the fault coverage are described. The limitations of these techniques and methods to overcome these limitations are presented.

UR - https://www.scopus.com/pages/publications/0029341651

UR - https://www.scopus.com/pages/publications/0029341651#tab=citedBy

U2 - 10.1109/82.401166

DO - 10.1109/82.401166

M3 - Article

AN - SCOPUS:0029341651

SN - 1057-7130

VL - 42

SP - 437

EP - 445

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IS - 7

ER -

Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy

Abstract

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