Fast-frequency offset cancellation loop using low-IF receiver and fractional-N PLL

Sangho Shin, Kyungmin Kim, Kwyro Lee, Sung Mo Kang

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60°. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-μm CMOS process, our circuit takes 30 μs to reject the frequency offset of +200 kHz within the accuracy of ±5 ppm, with 60-DFFs for a time-to-digital converter.

Original languageEnglish (US)
Pages (from-to)272-276
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number3
StatePublished - Mar 7 2007
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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