TY - JOUR
T1 - Design and Fabrication of Flow-Based Edge Detection Memristor Crossbar Circuits1
AU - Pannu, Jodh Singh
AU - Raj, Sunny
AU - Fernandes, Steven Lawrence
AU - Chakraborty, Dwaipayan
AU - Rafiq, Sarah
AU - Cady, Nathaniel
AU - Jha, Sumit Kumar
N1 - Funding Information:
ACKNOWLEDGMENT We acknowledge support from NSF Awards #1822976 and #1422257, an award from the Florida Cybersecurity Center, awards from the Royal Bank of Canada, and the Air Force Young Investigator Award to Sumit Jha. Dr. Steven Fernandes acknowledges support from the University of Central Florida Preeminent Post-doctoral Fellowship Program.
Funding Information:
Manuscript received February 2, 2020; accepted March 8, 2020. Date of publication March 30, 2020; date of current version May 6, 2020. This work was supported by NSF Awards from the Florida Cybersecurity Center, the Royal Bank of Canada, and the Air Force Young Investigator Award to Sumit Jha under Grant #1822976 and Grant #1422257. The work of Steven Lawrence Fernandes was supported by the University of Central Florida Preeminent Post-doctoral Fellowship Program. This brief was recommended by Associate Editors Yajun Ha and Edoardo Bonizzoni. (Corresponding author: Jodh Singh Pannu.) Jodh Singh Pannu, Sunny Raj, Steven Lawrence Fernandes, and Sumit Kumar Jha are with the Computer Science Department, University of Central Florida, Orlando, FL 32816 USA.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - We design and fabricate a flow-based circuit for edge detection in images that exploits device-level parallelism in nanoscale memristor crossbars. In our approach, a corpus of human-labeled edges in BSDS500 images is used to learn an edge detection function with ternary values: True, false, and don't-care. A Boolean crossbar design implementing an approximation of this ternary function using in-memory flow-based computing is then obtained using a massively parallel simulated annealing search executed on GPUs. We demonstrate the success of our approach by fabricating the memristor circuit on a 300mm wafer platform using a custom 65nm CMOS/ReRAM process technology. We demonstrate that our flow-based computing approach is either faster, more energy-efficient or produces fewer incorrect edges than other competing approaches. We show that our design has power and area requirements that are 3.3x and 2.5x lower, respectively, than the previous state-of-The-Art.
AB - We design and fabricate a flow-based circuit for edge detection in images that exploits device-level parallelism in nanoscale memristor crossbars. In our approach, a corpus of human-labeled edges in BSDS500 images is used to learn an edge detection function with ternary values: True, false, and don't-care. A Boolean crossbar design implementing an approximation of this ternary function using in-memory flow-based computing is then obtained using a massively parallel simulated annealing search executed on GPUs. We demonstrate the success of our approach by fabricating the memristor circuit on a 300mm wafer platform using a custom 65nm CMOS/ReRAM process technology. We demonstrate that our flow-based computing approach is either faster, more energy-efficient or produces fewer incorrect edges than other competing approaches. We show that our design has power and area requirements that are 3.3x and 2.5x lower, respectively, than the previous state-of-The-Art.
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U2 - 10.1109/TCSII.2020.2984155
DO - 10.1109/TCSII.2020.2984155
M3 - Article
AN - SCOPUS:85084398280
SN - 1549-7747
VL - 67
SP - 961
EP - 965
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 5
M1 - 9050658
ER -