Design and Analysis of a Hardware Accelerator with FPU-Based Runge-Kutta Solvers

In several high-speed computer applications, ordinary differential equations (ODEs) are often utilized. Modern CPUs, however, usually offer a modest throughput for these systems. This paper discusses the implemented design and analysis of a hardware accelerator including second-order, third-order, and fourth-order Runge-Kutta ODE solvers for improving the computing speed and accuracy. The implementation of the hardware accelerators has been done using the VHDL programming language and has been deployed on the Zynq ZC702 FPGA evaluation board. A comprehensive comparative analysis of different Runge-Kutta hardware accelerators, highlighting factors including timing performance, hardware resource usage, and the total on-chip power consumption has been given. According to the experimental findings, the fourth-order Runge-Kutta equation has a significant power consumption, rising by an estimated 51.37 percent and 12.445 percent when comparing second-order and third-order Runge-Kutta solvers at a clock rate of 100 MHz, respectively. This study contributes to the enhancement of ODE solutions in high-performance computing applications.