Complementary structure of memristive devices based passive memory arrays

Sangho Shin; Kyungmin Kim; Sung Mo Kang

doi:10.1109/ISCAS.2011.5937567

Complementary structure of memristive devices based passive memory arrays

Sangho Shin, Kyungmin Kim, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarily written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

Original language	English (US)
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	321-324
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937567
State	Published - 2011
Externally published	Yes
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: May 15 2011 → May 18 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	5/15/11 → 5/18/11

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2011.5937567

Cite this

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title = "Complementary structure of memristive devices based passive memory arrays",

abstract = "This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarily written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.",

author = "Sangho Shin and Kyungmin Kim and Kang, {Sung Mo}",

year = "2011",

doi = "10.1109/ISCAS.2011.5937567",

language = "English (US)",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "321--324",

booktitle = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011",

note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

Shin, S, Kim, K & Kang, SM 2011, Complementary structure of memristive devices based passive memory arrays. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937567, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 321-324, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 5/15/11. https://doi.org/10.1109/ISCAS.2011.5937567

Complementary structure of memristive devices based passive memory arrays. / Shin, Sangho; Kim, Kyungmin; Kang, Sung Mo.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 321-324 5937567 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Kyungmin

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AB - This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarily written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

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BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

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Complementary structure of memristive devices based passive memory arrays

Abstract

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All Science Journal Classification (ASJC) codes

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