TY - GEN
T1 - Complementary Commutation-Based Π-Type DC SSCB
AU - Kheirollahi, Reza
AU - Zhao, Shuyan
AU - Zhang, Hua
AU - Lu, Fei
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This digest introduces a new dc solid-state circuit breaker (SSCB) using a complementary commutation technique. The proposed SSCB employs a capacitor-capacitor pair topology in a Π structure, called II-type SSCB. The capacitor-capacitor pair structure helps to achieve a reliable and fast re-closing and re-breaking process. The presented topology mostly benefits from its simplicity. It removes the voltage on passive components during the SSCB OFF-state, which enhances reliability. The II-type SSCB needs no charge/discharge circuits, and it solely depends on the dc system itself. In addition, the introduced SSCB facilities using high-power rating thyristors in the main and auxiliary branches, making it one of the best solutions for medium-voltage section. Two modified topologies are also presented to extend the applications of II-type SSCB in practice. To verify the effectiveness of the proposed topology, experiments of 500 V/50 A prototype are conducted. The results show the reaction time interval of 42 μs under load current interruption, where the peak voltage on the main and auxiliary thyristors reaches 581 V and 500 V, respectively.
AB - This digest introduces a new dc solid-state circuit breaker (SSCB) using a complementary commutation technique. The proposed SSCB employs a capacitor-capacitor pair topology in a Π structure, called II-type SSCB. The capacitor-capacitor pair structure helps to achieve a reliable and fast re-closing and re-breaking process. The presented topology mostly benefits from its simplicity. It removes the voltage on passive components during the SSCB OFF-state, which enhances reliability. The II-type SSCB needs no charge/discharge circuits, and it solely depends on the dc system itself. In addition, the introduced SSCB facilities using high-power rating thyristors in the main and auxiliary branches, making it one of the best solutions for medium-voltage section. Two modified topologies are also presented to extend the applications of II-type SSCB in practice. To verify the effectiveness of the proposed topology, experiments of 500 V/50 A prototype are conducted. The results show the reaction time interval of 42 μs under load current interruption, where the peak voltage on the main and auxiliary thyristors reaches 581 V and 500 V, respectively.
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U2 - 10.1109/APEC43580.2023.10131262
DO - 10.1109/APEC43580.2023.10131262
M3 - Conference contribution
AN - SCOPUS:85162242380
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 514
EP - 519
BT - APEC 2023 - 38th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2023
Y2 - 19 March 2023 through 23 March 2023
ER -