@inproceedings{d623a2c104cf46a69fc63f14c568a5d9,
title = "A pipelined 9-stage video-rate analog-to-digital converter",
abstract = "The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9-μm CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm2 and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures.",
author = "Lewis, {Stephen H.} and Fetterman, {H. Scott} and Gross, {George F.} and R. Ramachandran and Viswanathan, {T. R.}",
year = "1991",
language = "English (US)",
isbn = "0780300157",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Publ by IEEE",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",
note = "Proceedings of the IEEE 1991 Custom Integrated Circuits Conference ; Conference date: 12-05-1991 Through 15-05-1991",
}