A pipelined 9-stage video-rate analog-to-digital converter

Stephen H. Lewis, H. Scott Fetterman, George F. Gross, R. Ramachandran, T. R. Viswanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9-μm CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm2 and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780300157
StatePublished - Dec 1 1991
Externally publishedYes
EventProceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: May 12 1991May 15 1991

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherProceedings of the IEEE 1991 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period5/12/915/15/91

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A pipelined 9-stage video-rate analog-to-digital converter'. Together they form a unique fingerprint.

Cite this