A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge

Dwaipayan Chakraborty; Sunny Raj; Sumit Kumar Jha

doi:10.1109/NANOARCH.2017.8053712

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge

Dwaipayan Chakraborty, Sunny Raj, Sumit Kumar Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman Grand Prize. The potential availability of sub-5nm nanoscale memristors and single-molecule diode devices coupled with the ability to fabricate high-density nanoscale memristor crossbars suggests that our design may eventually be fabricated to meet the size constraints of the Feynman Grand Prize.

Original language	English (US)
Title of host publication	Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	67-72
Number of pages	6
ISBN (Electronic)	9781509060368
DOIs	https://doi.org/10.1109/NANOARCH.2017.8053712
State	Published - Sep 28 2017
Externally published	Yes
Event	2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 - Newport, United States Duration: Jul 25 2017 → Jul 26 2017

Publication series

Name	Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

Conference

Conference	2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017
Country/Territory	United States
City	Newport
Period	7/25/17 → 7/26/17

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Computer Networks and Communications

Access to Document

10.1109/NANOARCH.2017.8053712

Cite this

Chakraborty, D., Raj, S., & Jha, S. K. (2017). A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 (pp. 67-72). Article 8053712 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NANOARCH.2017.8053712

Chakraborty, Dwaipayan ; Raj, Sunny ; Jha, Sumit Kumar. / A compact 8-bit adder design using in-memory memristive computing : Towards solving the Feynman Grand Prize challenge. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 67-72 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017).

@inproceedings{cb90713fa7fe402888fcecb63380400f,

title = "A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge",

abstract = "We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman Grand Prize. The potential availability of sub-5nm nanoscale memristors and single-molecule diode devices coupled with the ability to fabricate high-density nanoscale memristor crossbars suggests that our design may eventually be fabricated to meet the size constraints of the Feynman Grand Prize.",

author = "Dwaipayan Chakraborty and Sunny Raj and Jha, {Sumit Kumar}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017 ; Conference date: 25-07-2017 Through 26-07-2017",

year = "2017",

month = sep,

day = "28",

doi = "10.1109/NANOARCH.2017.8053712",

language = "English (US)",

series = "Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "67--72",

booktitle = "Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017",

address = "United States",

}

Chakraborty, D, Raj, S & Jha, SK 2017, A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge. in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017., 8053712, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Institute of Electrical and Electronics Engineers Inc., pp. 67-72, 2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, United States, 7/25/17. https://doi.org/10.1109/NANOARCH.2017.8053712

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge. / Chakraborty, Dwaipayan; Raj, Sunny; Jha, Sumit Kumar.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 67-72 8053712 (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A compact 8-bit adder design using in-memory memristive computing

T2 - 2017 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

AU - Chakraborty, Dwaipayan

AU - Raj, Sunny

AU - Jha, Sumit Kumar

PY - 2017/9/28

Y1 - 2017/9/28

N2 - We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman Grand Prize. The potential availability of sub-5nm nanoscale memristors and single-molecule diode devices coupled with the ability to fabricate high-density nanoscale memristor crossbars suggests that our design may eventually be fabricated to meet the size constraints of the Feynman Grand Prize.

AB - We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman Grand Prize. The potential availability of sub-5nm nanoscale memristors and single-molecule diode devices coupled with the ability to fabricate high-density nanoscale memristor crossbars suggests that our design may eventually be fabricated to meet the size constraints of the Feynman Grand Prize.

UR - http://www.scopus.com/inward/record.url?scp=85034763040&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85034763040&partnerID=8YFLogxK

U2 - 10.1109/NANOARCH.2017.8053712

DO - 10.1109/NANOARCH.2017.8053712

M3 - Conference contribution

AN - SCOPUS:85034763040

T3 - Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

SP - 67

EP - 72

BT - Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 July 2017 through 26 July 2017

ER -

Chakraborty D, Raj S, Jha SK. A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 67-72. 8053712. (Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017). doi: 10.1109/NANOARCH.2017.8053712

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge

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