Abstract
A 270MHz frequency synthesizer/FSK modulator for low-rate WPAN is implemented. It consumes only 4.9mW adopting current re-using technique, self-DC biasing scheme, and appropriate divider architecture. The 3 rd-order feedback type DSM and the high performance charge pump are designed for wide loop bandwidth, which enables to design a low power and low noise frequency synthesizer. The implemented prototype offers 500kHz-loop bandwidth and -104dBc/Hz in-band noise. It also plays a role as a FSK modulator which shows only 1.1 dB degradation at 10-3 symbol BER compared with the ideal FSK-modulator.
Original language | English (US) |
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Pages | 443-446 |
Number of pages | 4 |
State | Published - 2003 |
Externally published | Yes |
Event | 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Philadelphia, PA, United States Duration: Jun 8 2003 → Jun 10 2003 |
Other
Other | 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium |
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Country/Territory | United States |
City | Philadelphia, PA |
Period | 6/8/03 → 6/10/03 |
All Science Journal Classification (ASJC) codes
- General Engineering