A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration

Yong Sin Kim; Sangho Shin; Sung Mo Kang

A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration

Yong Sin Kim, Sangho Shin, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes a high speed current mode multi-level simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to ±2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18μm CMOS process show that the proposed design achieves 4-Gb/s/pin data rate with 512ps timing window and 27mV voltage window. I/O circuits consume 12mW/pin at a supply voltage of 1V.

Original language	English (US)
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	1007-1010
Number of pages	4
State	Published - 2006
Externally published	Yes
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: May 21 2006 → May 24 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	5/21/06 → 5/24/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{8f811b67d6e041c1898d09cb8c3fc8da,

title = "A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration",

abstract = "This paper describes a high speed current mode multi-level simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to ±2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18μm CMOS process show that the proposed design achieves 4-Gb/s/pin data rate with 512ps timing window and 27mV voltage window. I/O circuits consume 12mW/pin at a supply voltage of 1V.",

author = "Kim, {Yong Sin} and Sangho Shin and Kang, {Sung Mo}",

year = "2006",

language = "English (US)",

isbn = "0780393902",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1007--1010",

booktitle = "ISCAS 2006",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

}

Kim, YS, Shin, S & Kang, SM 2006, A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1692758, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1007-1010, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 5/21/06.

A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. / Kim, Yong Sin; Shin, Sangho; Kang, Sung Mo.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 1007-1010 1692758 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration

AU - Kim, Yong Sin

AU - Shin, Sangho

AU - Kang, Sung Mo

PY - 2006

Y1 - 2006

N2 - This paper describes a high speed current mode multi-level simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to ±2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18μm CMOS process show that the proposed design achieves 4-Gb/s/pin data rate with 512ps timing window and 27mV voltage window. I/O circuits consume 12mW/pin at a supply voltage of 1V.

AB - This paper describes a high speed current mode multi-level simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to ±2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18μm CMOS process show that the proposed design achieves 4-Gb/s/pin data rate with 512ps timing window and 27mV voltage window. I/O circuits consume 12mW/pin at a supply voltage of 1V.

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M3 - Conference contribution

AN - SCOPUS:34547300678

SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1007

EP - 1010

BT - ISCAS 2006

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration

Abstract

Publication series

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All Science Journal Classification (ASJC) codes

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