A 10-b 20-Msample/s Analog-to-Digital Converter

Stephen H. Lewis; H. Scott Fetterman; George F. Gross; R. Ramachandran; T. R. Viswanathan

doi:10.1109/4.121557

A 10-b 20-Msample/s Analog-to-Digital Converter

Stephen H. Lewis
, H. Scott Fetterman
, George F. Gross
, R. Ramachandran
, T. R. Viswanathan

Research output: Contribution to journal › Article › peer-review

415 Scopus citations

Abstract

This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm² and dissipates 240 mW.

Original language	English (US)
Pages (from-to)	351-358
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	3
DOIs	https://doi.org/10.1109/4.121557
State	Published - Mar 1992
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.121557

Cite this

@article{ff89f015e049428cbdec101912b5cadb,

title = "A 10-b 20-Msample/s Analog-to-Digital Converter",

abstract = "This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.",

author = "Lewis, \{Stephen H.\} and Fetterman, \{H. Scott\} and Gross, \{George F.\} and R. Ramachandran and Viswanathan, \{T. R.\}",

year = "1992",

month = mar,

doi = "10.1109/4.121557",

language = "English (US)",

volume = "27",

pages = "351--358",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A 10-b 20-Msample/s Analog-to-Digital Converter

AU - Lewis, Stephen H.

AU - Fetterman, H. Scott

AU - Gross, George F.

AU - Ramachandran, R.

AU - Viswanathan, T. R.

PY - 1992/3

Y1 - 1992/3

N2 - This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.

AB - This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.

UR - https://www.scopus.com/pages/publications/0026836960

UR - https://www.scopus.com/pages/publications/0026836960#tab=citedBy

U2 - 10.1109/4.121557

DO - 10.1109/4.121557

M3 - Article

AN - SCOPUS:0026836960

SN - 0018-9200

VL - 27

SP - 351

EP - 358

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 3

ER -

A 10-b 20-Msample/s Analog-to-Digital Converter

Abstract

All Science Journal Classification (ASJC) codes

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