This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering