A 10-b 20-Msample/s Analog-to-Digital Converter

Stephen H. Lewis; H. Scott Fetterman; George F. Gross; R. Ramachandran; T. R. Viswanathan

doi:10.1109/4.121557

A 10-b 20-Msample/s Analog-to-Digital Converter

Stephen H. Lewis, H. Scott Fetterman, George F. Gross, R. Ramachandran, T. R. Viswanathan

Research output: Contribution to journal › Article › peer-review

411 Scopus citations

Abstract

This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm² and dissipates 240 mW.

Original language	English (US)
Pages (from-to)	351-358
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	3
DOIs	https://doi.org/10.1109/4.121557
State	Published - Mar 1992
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.121557

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A 10-b 20-Msample/s Analog-to-Digital Converter

Abstract

All Science Journal Classification (ASJC) codes

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