A 10-b 20-Msample/s Analog-to-Digital Converter

Stephen H. Lewis, H. Scott Fetterman, George F. Gross, R. Ramachandran, T. R. Viswanathan

Research output: Contribution to journalArticlepeer-review

377 Scopus citations

Abstract

This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.

Original languageEnglish (US)
Pages (from-to)351-358
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number3
DOIs
StatePublished - Mar 1992

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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