Abstract
A new frequency synthesizer with low-power and short settling time is introduced. With two-point channel controls for an integer-N PLL, we have achieved a near zero settling time for any frequency change in 2.4GHz ZigBee band. By utilizing a vertical-NPN parasitic transistor for the VCO biasing, the closein phase noise has been improved by 5dB from the case of MOS biasing. A modifled-TSPC topology is proposed for low-voltage frequency divider circuits. Using the 1.2V supply voltage for 0.18μm CMOS, the power consumption is only 4.2mW and the phase noise is -116.5dBc/Hz at 1MHz offset.
Original language | English (US) |
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Article number | 4014918 |
Pages (from-to) | 411-414 |
Number of pages | 4 |
Journal | IEEE MTT-S International Microwave Symposium Digest |
DOIs | |
State | Published - 2006 |
Externally published | Yes |
Event | 2006 IEEE MTT-S International Microwave Symposium Digest - San Francisco, CA, United States Duration: Jun 11 2006 → Jun 16 2006 |
All Science Journal Classification (ASJC) codes
- Radiation
- Condensed Matter Physics
- Electrical and Electronic Engineering