4.2mW CMOS frequency synthesizer for 2.4GHz ZigBee application with fast settling time performance

Sangho Shin, Kwyro Lee, Sung Mo Kang

Research output: Contribution to journalConference article

23 Scopus citations

Abstract

A new frequency synthesizer with low-power and short settling time is introduced. With two-point channel controls for an integer-N PLL, we have achieved a near zero settling time for any frequency change in 2.4GHz ZigBee band. By utilizing a vertical-NPN parasitic transistor for the VCO biasing, the closein phase noise has been improved by 5dB from the case of MOS biasing. A modifled-TSPC topology is proposed for low-voltage frequency divider circuits. Using the 1.2V supply voltage for 0.18μm CMOS, the power consumption is only 4.2mW and the phase noise is -116.5dBc/Hz at 1MHz offset.

Original languageEnglish (US)
Article number4014918
Pages (from-to)411-414
Number of pages4
JournalIEEE MTT-S International Microwave Symposium Digest
DOIs
StatePublished - Dec 1 2006
Event2006 IEEE MTT-S International Microwave Symposium Digest - San Francisco, CA, United States
Duration: Jun 11 2006Jun 16 2006

All Science Journal Classification (ASJC) codes

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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