3.48mW 2.4GHz range frequency synthesizer architecture with two-point channel control for fast settling performance

Sangho Shin, Kwyro Lee, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A new frequency synthesizer architecture with low-power and very short settling time is introduced for 2.4GHz ZigBee applications. It uses two-point channel control with divider control and direct VCO control. A DAC with tunable gain is used along with a linearized varactor for the direct VCO control path. Despite the use of an integer-N architecture with 50kHz loop bandwidth, we have achieved a frequency settling time of less than 10μsec for 80MHz frequency jumping from 2400MHz. The proposed modified-TSPC circuit topology with 2-transistor stacks operational with lower supply voltage is used for the high frequency divider circuits. With a lowered supply voltage of 1.0V, the power consumption is significantly reduced and so is the switching noise induced by TSPC and digital circuits. With the -112 dBc/Hz phase noise at 1MHz offset from 2.44GHz, total power consumption using 0.18μm CMOS technology is only 3.48mW.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages3-6
Number of pages4
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Publication series

NameProceedings - IEEE International SOC Conference

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period9/25/059/28/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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