@inproceedings{6b7f4d5d777340c481c20400090f0815,
title = "3.48mW 2.4GHz range frequency synthesizer architecture with two-point channel control for fast settling performance",
abstract = "A new frequency synthesizer architecture with low-power and very short settling time is introduced for 2.4GHz ZigBee applications. It uses two-point channel control with divider control and direct VCO control. A DAC with tunable gain is used along with a linearized varactor for the direct VCO control path. Despite the use of an integer-N architecture with 50kHz loop bandwidth, we have achieved a frequency settling time of less than 10μsec for 80MHz frequency jumping from 2400MHz. The proposed modified-TSPC circuit topology with 2-transistor stacks operational with lower supply voltage is used for the high frequency divider circuits. With a lowered supply voltage of 1.0V, the power consumption is significantly reduced and so is the switching noise induced by TSPC and digital circuits. With the -112 dBc/Hz phase noise at 1MHz offset from 2.44GHz, total power consumption using 0.18μm CMOS technology is only 3.48mW.",
author = "Sangho Shin and Kwyro Lee and Kang, {Sung Mo}",
year = "2005",
language = "English (US)",
isbn = "0780392647",
series = "Proceedings - IEEE International SOC Conference",
pages = "3--6",
editor = "D. Ha and R. Krishnamurthy and S. Kim and A. Marshall",
booktitle = "Proceedings - IEEE International SOC Conference, 2005 SOCC",
note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",
}