@inproceedings{c831b11a74a346bb9426eeeab3227ef0,
title = "2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop",
abstract = "This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a {\'O}{\"A} fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a Frequency/Phase Detector (PFD) and a new non-uniform resolution Time-to-Dlgital Converter (TDC). By adopting the weighted delaylength for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of Ins. For the 24GHz ZigBee transceiver with 4MHz IF, designed for 0.18um CMOLS process, the frequency offset cancellation time takes about 30us under the PLL loopbandwidth of 100 kHz.",
author = "Sangho Shin and Kwyro Lee and Kang, {Sung Mo}",
year = "2006",
language = "English (US)",
isbn = "0780393902",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "97--100",
booktitle = "ISCAS 2006",
note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",
}