2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop

Sangho Shin, Kwyro Lee, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a ÓÄ fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a Frequency/Phase Detector (PFD) and a new non-uniform resolution Time-to-Dlgital Converter (TDC). By adopting the weighted delaylength for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of Ins. For the 24GHz ZigBee transceiver with 4MHz IF, designed for 0.18um CMOLS process, the frequency offset cancellation time takes about 30us under the PLL loopbandwidth of 100 kHz.

Original languageEnglish (US)
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages97-100
Number of pages4
StatePublished - Dec 1 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: May 21 2006May 24 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period5/21/065/24/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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